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Every time you ask ChatGPT a question, your request triggers a data relay race. Information leaves memory, passes through a CPU for preprocessing, travels to a GPU for heavy computation, and then makes its way back \u2014 and that entire journey repeats for every single word the AI generates.<\/p>\n
The bottleneck is structural \u2014 it means routing through some of the most expensive and power-intensive chips in the industry on every single request. That inefficiency is exactly what XCENA<\/a>, a startup with offices in South Korea and the U.S., is trying to solve. The four-year-old startup has designed a chip that places compute capabilities much closer to DRAM \u2014 the fast, short-term memory chips that store data a processor is actively using \u2014 allowing routine data operations to be handled near memory, without the costly round trips between CPUs, GPUs, and memory. <\/p>\n If it works at scale, the implications for AI infrastructure costs could be significant, which largely explains investor enthusiasm around the country. Indeed, XCENA just raised $135 million in a Series B at a valuation of $570 million, bringing its total raised to $185 million. <\/p>\n XCENA CEO Jin Kim co-founded the startup in 2022 alongside CTO Dohun Kim and CPO Harry Juhyun Kim, all veterans of Samsung and SK Hynix, the memory giants that supply chips powering Nvidia\u2019s GPUs. \u201cCPUs and GPUs have both gotten smarter over the decades. Memory never did. XCENA wants to change that,\u201d Kim said in an interview with TechCrunch. \u201cThe recent rise in memory prices and related stocks points to a broader shift in AI infrastructure toward memory-centric architectures,\u201d he added. (This month, the three companies that dominate the global memory chip market \u2014 Samsung, SK Hynix, and Micron \u2014 each crossed a trillion-dollar valuation for the first time.)<\/p>\n XCENA is betting its business on the thesis that \u201cinference isn\u2019t just a compute problem; it\u2019s increasingly a memory scaling problem,\u201d said Kim.<\/p>\n XCENA\u2019s chip, the MX1, connects to the CPU through CXL (Compute Express Link) \u2014 essentially a dedicated express lane between the processor and memory \u2014 processing data before it ever needs to leave the memory module. It brings compute to the data, not the other way around. The company claims that what used to require 10 servers could potentially run on just one.<\/p>\n \u201cWhile GPUs excel at matrix multiplication \u2014 the heavy math behind AI model training \u2014 much of the surrounding data orchestration, including preprocessing, KV cache management [the system that stores prior conversation context so a model doesn\u2019t have to reprocess it], and data caching, still runs on CPUs. Our chip handles those tasks directly within the memory module itself,\u201d Kim said.<\/p>\n Demand for memory solutions has surged since the second half of last year, and the company believes the timing is working in its favor.<\/p>\n Conversations with several global memory vendors are in early stages, though Kim declined to name them. The company\u2019s ideal customers are hyperscalers spending tens of billions a year on AI infrastructure, where even a small gain in memory efficiency can mean hundreds of millions in savings.<\/p>\n The MX1 is still a prototype. Mass production chips are scheduled to roll off Samsung\u2019s foundry lines by the end of 2026, with the company expecting to generate revenue starting in 2027.<\/p>\n While neural processing unit (NPU) makers are competing to challenge Nvidia for training workloads, XCENA is targeting the memory-intensive layer that sits underneath all of it.<\/p>\n XCENA\u2019s closest rivals include Astera Labs and Marvell, both Nasdaq-listed companies working on next-generation memory connectivity. Marvell is a large, established player already working in the same space, Kim said, adding that the differentiator comes down to intellectual property. \u201cWe have thousands of cores,\u201d Kim said. Based on public specs, Marvell\u2019s approach relies on a handful of general-purpose cores by comparison.<\/p>\n Those cores are built on RISC-V \u2014 an open-source chip design blueprint \u2014 and optimized specifically for data processing,<\/strong> with each core deliberately kept small and efficient. Beyond the cores themselves, XCENA designs its own internal memory hierarchy, interconnect bus, and DRAM controller \u2014 a level of vertical integration that most chip companies, including larger rivals, typically outsource.<\/p>\n Seoul-based VC firms Altinum and IMM Investment co-led the Series B round, along with Corstone Asia and existing investors SBI Investment and Mirae Asset Capital. The company, which has more than 90 staff across offices in Pangyo, a tech hub outside Seoul, and in Sunnyvale, is also in conversations with international investors about additional funding.<\/p>\n<\/div>\n When you purchase through links in our articles, we may earn a small commission<\/a>. This doesn\u2019t affect our editorial independence.<\/em><\/p>\n